An electronic computer-aided design (“E-CAD”) tool is used to create a circuit design, including a very large scale integration (“VLSI”) circuit design. The circuit design includes a netlist, which defines a collection of nets specific to the circuit design. Each “net” is a single electrical path in a circuit that has the same electrical characteristics at all of its points. For example, a collection of wires that carries the same signal between components is a net. If the components allow the signal to pass through unaltered (as in the case of a terminal), then the net continues on subsequently connected wires. If, however, the component modifies the signal (as in the case of a transistor or a logic gate), then the net terminates at that component and a new net begins on the other side. A “net name” identifies a particular net within the netlist. Components are identified within the circuit design as ‘design elements’.
A significant characteristic of VLSI and other types of circuit design is a reliance on hierarchical description. A primary reason for using hierarchical description is to hide the vast amount of detail in a design. By reducing the distracting detail to a single object that is lower in the hierarchy, one can greatly simplify many E-CAD operations. For example, simulation, verification, design-rule checking, and layout constraints can all benefit from hierarchical representation, which makes them more computationally tractable. Since many circuit designs are too complicated to be easily considered in their totality, a complete design is often viewed as a collection of design element aggregates that are further divided into sub-aggregates in a recursive and hierarchical manner. In VLSI circuit designs, these aggregates are commonly referred to as design blocks (or cells). The use of a design block at a given level of hierarchy is called an ‘instance’. Each design block has one or more ‘ports’, each of which provides a connection point between a net within the design block and a net external to the design block. A net connected to a port in a design block is termed a ‘ported’ net.
A Highest Level Signal Name (“HLSN”) is the unique signal name that identifies a collection of connected nets or ‘hierarchical net pieces’. For example, a hierarchical net piece is a ported net in a design block; the ported net connects to a ported net of another design block to form the HLSN. The HLSN derives its identity from the name of the hierarchical net piece at the highest hierarchical level in the circuit design.
Typically, during analysis of a circuit design, an E-CAD analysis tool (e.g., an analysis tool that analyzes a circuit design to estimate field effect transistor (“FET”) leakage currents) determines an HLSN for a particular net in the circuit design. Configuration commands and other parameters of the circuit design are often specified using a net's HLSN as a reference. It is therefore important to identify the HLSN for any given net to determine if a particular configuration command is applicable to the net. In one example, the E-CAD analysis tool, during analysis of the circuit design, reaches a transistor terminal (or other device terminal) at one hierarchical level of the circuit design. The HLSN of one or more nets connected to other terminals of the transistor is needed to apply appropriate configuration commands. Further, on completion of the analysis, the analysis results are often reported relative to each HLSN in the circuit design, since such information is often more useful to design engineers than information relating to individual nets of the circuit design.
Prior art E-CAD analysis tools typically generate a ‘map’ relating each net (by the identifying net name) to its corresponding HLSN. Where the circuit design comprises billions of components, this mapping process takes a significant amount of time and consumes a substantial amount of memory. Thus, the design process is delayed and computer resources are committed to the map, reducing resource availability to other tools and programs.